Další příklad kódu ve VHDL pro FGPA. Tentokrát 8bitový čítač/counter
Budou zde zobrazeny dva zdrojové kódy, v prvním je podmínka:
if (reset =’1′) then
to znamená, že čítač bude v resetu, dokud bude vstup „reset“ v logické 1.
Ve druhém příkladu je tato podmínka upravena:
if (reset =’1′ AND reset’event) then
to znamená, že reset vyresetuje čítač pouze tehdy, pokud bude vstup „reset“ v logické 1 A ZÁROVEŇ nastane na tomto vstupu změna stavu.
Obě tyto podmínky vysvětlují i obrázky ze simulace.
První příklad:
counter.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port(
clk : in std_logic;
reset : in std_logic;
output : out std_logic_vector (7 downto 0)
);
end counter;
architecture behavioral of counter is
signal counter : std_logic_vector (7 downto 0) := „00000000“; –incializace signalu counter
begin
output <= counter; — do vystupu output predej data z counter
process (clk, reset) –proces se provede pokud bude nejaka zmena na clk a reset
begin
if (reset =’1′) then — pokud je reset v ‚1‘, tak resetuj citac
counter <= „00000000“;
elsif rising_edge(CLK) then — pokud je na clk nabezna hrana, tak pricti k counter + 1
counter <= counter + 1;
end if;
end process;
end behavioral; –konec architektury
counter_tb.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_tb is
end counter_tb;
architecture tb of counter_tb is
component counter –deklarace komponenty counter
port(
clk : in std_logic;
reset : in std_logic;
output : out std_logic_vector (7 downto 0)
);
end component; –konec deklarace komponenty
signal clk : std_logic := ‚0‘; –incializace signalu
signal reset : std_logic := ‚0‘;
signal output : std_logic_vector (7 downto 0) :=“00000000″;
begin
dut : counter port map
(
clk => clk,
reset => reset,
output => output
);
process
begin
clk <= ‚0‘;
reset <= ‚1‘;
wait for 10ns;
reset <= ‚0‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 5ns;
reset <= ‚1‘; –zapni reset
wait for 5ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
wait;
end process;
end;
Druhý příklad:
counter.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port(
clk : in std_logic;
reset : in std_logic;
output : out std_logic_vector (7 downto 0)
);
end counter;
architecture behavioral of counter is
signal counter : std_logic_vector (7 downto 0) := „00000000“; –incializace signalu counter
begin
output <= counter; — do vystupu output predej data z counter
process (clk, reset) –proces se provede pokud bude nejaka zmena na clk a reset
begin
if (reset =’1′ AND reset’event) then — pokud je reset v ‚1‘ A ZAROVEN nastala zmena, tak resetuj citac
counter <= „00000000“;
elsif rising_edge(CLK) then — pokud je na clk nabezna hrana, tak pricti k counter + 1
counter <= counter + 1;
end if;
end process;
end behavioral; –konec architektury
counter_tb.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_tb is
end counter_tb;
architecture tb of counter_tb is
component counter –deklarace komponenty counter
port(
clk : in std_logic;
reset : in std_logic;
output : out std_logic_vector (7 downto 0)
);
end component; –konec deklarace komponenty
signal clk : std_logic := ‚0‘; –incializace signalu
signal reset : std_logic := ‚0‘;
signal output : std_logic_vector (7 downto 0) :=“00000000″;
begin
dut : counter port map
(
clk => clk,
reset => reset,
output => output
);
process
begin
clk <= ‚0‘;
reset <= ‚1‘;
wait for 10ns;
reset <= ‚0‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 5ns;
reset <= ‚1‘; –zapni reset
wait for 5ns;
clk <= ‚1‘;
wait for 10ns;
clk <= ‚0‘;
wait for 10ns;
clk <= ‚1‘;
wait for 10ns;
wait;
end process;
end;